Dynamic random access memory (DRAM) circuits are used extensively in the electronics industry for storing data. Each memory cell consists of a single capacitor and a field effect transistor as a charge transfer transistor.
Currently, the contact plug of the DRAM is formed by chemical vapor deposition (CVD) followed by physical vapor deposition (PVD). Such a two-step process is necessary because severe surface roughness on the upper surface of a conductive surface formed by CVD is difficult to directly pattern using photolithography and etching processes.
However, the two-step process for forming the conductive layer is complicated and expensive, and the grain sizes of the conductive layers formed by PVD and the CVD are different. As a result, the interface between the conductive layers formed by CVD and PVD can easily incur a necking connection and cause high resistance or pattern toppling in the subsequent processes, such as lithography and etching processes.
This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.